suhas_shiv
Full Member level 2
Hi All,
The first stage of a pipeline ADC decides its resolultion mostly. Hence what I want to ask is what are some precautions and circuit pitfalls that I need to know about so that I can design one effectively. My resolution is 8 bits with a 40MhZ sampling.
Appreciate if anyone can give me some ideas to design a near ideal stage.
Thanks.
The first stage of a pipeline ADC decides its resolultion mostly. Hence what I want to ask is what are some precautions and circuit pitfalls that I need to know about so that I can design one effectively. My resolution is 8 bits with a 40MhZ sampling.
Appreciate if anyone can give me some ideas to design a near ideal stage.
Thanks.