Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

About first Stage of pipeline

Status
Not open for further replies.
S

suhas_shiv

Full Member level 2
Joined
Nov 30, 2005
Messages
136
Helped
11
Reputation
22
Reaction score
4
Trophy points
1,298
Activity points
2,461
Hi All,

The first stage of a pipeline ADC decides its resolultion mostly. Hence what I want to ask is what are some precautions and circuit pitfalls that I need to know about so that I can design one effectively. My resolution is 8 bits with a 40MhZ sampling.

Appreciate if anyone can give me some ideas to design a near ideal stage.

Thanks.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top