Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

will decouple caps do harm to high speed signals?

Status
Not open for further replies.
N

newbie_1

Member level 3
Joined
Sep 27, 2005
Messages
54
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,739
hi,

in layout, if decouple caps are under high speed signals which run at the speed of about 2G, will the caps attribute any noise to the high speed signals?

thanks

newbie
 

Genarally they can. Capacitors and power plate acts like R-L-C circuits, but with different resonant freq. At the point where this two characteristics are cut, you could have peaking. You can find this in Montrose book on this forum.
 

where do u put the decoupling caps? if u are talking about on the supply or some DC voltage bias, it should help to immune noise.
 

pixel said:
Genarally they can. Capacitors and power plate acts like R-L-C circuits, but with different resonant freq. At the point where this two characteristics are cut, you could have peaking. You can find this in Montrose book on this forum.
Click to expand...

thanks pixel, do you mean as long as the rlc frequency is far below the frequency of the signals then putting the caps under the signals will be ok?
 

Read chapter 5-Decoupling:
 

thanks pixel,

if the cap are under the signals, then the parasitic caps between the signals and the layer of decoupling capacitors will be greater than the that while cap not under the signals?

thanks
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top