ee484
Full Member level 3
hi, all.
If I have to design class A amplifier driving 4Ohm resistive load. Assuming the simple topology of class is bias current in the upper side and NMOS transistor in the lower side.
Say, I have output swing of 2V (output 3V process). Then, the voltage gain of the class A stage is roughly (assuming gm=20mS) 20mS*4 = 80mV/V. Then, the input of the gate should be 25V??
Waiting for your explanations.
Thanks,
B
If I have to design class A amplifier driving 4Ohm resistive load. Assuming the simple topology of class is bias current in the upper side and NMOS transistor in the lower side.
Say, I have output swing of 2V (output 3V process). Then, the voltage gain of the class A stage is roughly (assuming gm=20mS) 20mS*4 = 80mV/V. Then, the input of the gate should be 25V??
Waiting for your explanations.
Thanks,
B