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The difference between functional and gate-level verificatio

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steven852

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One more question tonight:

For functional verification, we use testbench to verify the function valid or not. After pass functional verification, we would go ahead with synthesis and P&R etc. At this moment, the synthesis can verify timing, area, power etc. But how do we verify function at gate-level?

Thanks
 

Re: The difference between functional and gate-level verific

Synthesis cant ensure functionality as design is transfeered from high level RTL to low level gate specifications.
Also for asynch timings gate sim is required.
 

Re: The difference between functional and gate-level verific

Functional verification tests the functionality of the design in RTL level. The same tests which are written for FV on RTL are supposed to be run on gate level netlist which is obtained after running synthesis. This is called Gate-Level Simulations.

Those tests which are passed on RTL are supposed to pass on netlist also. If not it indicates that there is some difference from RTL to available netlist(i.e., available netlist is not having intended functionality as RTL). This needs to be taken care.
 

Re: The difference between functional and gate-level verific

steven852 said:
One more question tonight:

For functional verification, we use testbench to verify the function valid or not. After pass functional verification, we would go ahead with synthesis and P&R etc. At this moment, the synthesis can verify timing, area, power etc. But how do we verify function at gate-level?

Thanks
Click to expand...

Functional verification pass doesn't mean your code is good nor does mean your synthesized netlist is what you desire.

If you want to ensure that the synthesized netlist is the same or the expected one with your RTL version, you shall strictly adhere to the good coding styles.

As for netlist's function, you may used formatlity to verify the netlist's functionality is the same with your RTL's; however I've not so much experience to tell you when this technique doens't work well.

If you still like to using dynamic simulation strategy to verify your netlist's validty, then you can uncover many unexpected behaviors aroused by your bad coding styles which make your dynamic simulation fail.

Suggestions: you can refer to some good books conncening with this topic including the write testbench and others related.

Thomson
 

Re: The difference between functional and gate-level verific

Could any body tell me what are the things to be noted if u want to use the same testbench for RTL as well as gate level simulation.

i.e we will have input delay and output delay to be applied for gate level simulation...how would you apply these parameters in ate level simulation??

Would like to hear some commments!!!

Regards,
dcreddy
 

Can anybody tell how the gatelevel simulation process is done ? all the answers are very generic. is it correct to say that the sdf file of the netlist for a particular technology is connected to it and the same testbench is run ?

is this the right way to run gate level simulation ?
 

use Verplex to do the RTL and gate equivalent check then if identical then the they should function the same.
 

@sree205
I think the synthesis tools generate SDF (back) annotated verilog netlist (which has all the technology specific timing information). You can use this netlist instead of RTL in the testbench and run all the tests developed for RTL. These simulations are called gate-level sims (and they all should PASS provided there is no problem).

@love2read
you can use Synopsys Formality as well for equivalancy checking ...
 

Re: The difference between functional and gate-level verific

The same test bench will be used to verify the gate-level netllist
i.e put the gate level netlist and the same test bench used earlier for RTL code
 

Re: The difference between functional and gate-level verific

naveen reddy said:
The same test bench will be used to verify the gate-level netllist
i.e put the gate level netlist and the same test bench used earlier for RTL code
Click to expand...

Will we need to add some input delays to the netlist when using the same RTL testbench for simulating it ? .. or just instantiate the the netlist in the testbench instead of the RTL top-level block ? ... something like using a different architecture for the same component (top-level) : one is RTL and some other time is netlist ..
 

Re: The difference between functional and gate-level verific

In general (It depends on corporate choice), we have to pass functional verification on RTL, to verify gate netlist we make do with equivalence checking RTL2gate, for several reasons, the main is that gate simulation need more processing resources, hence more time.

But, gate simulations are still required in some cases, for example :

- To simulate ATPG patterns (TDLs).
- To validate functioning of basic circuit features that allow ATE tests (JTAG,...)
 

Re: The difference between functional and gate-level verific

If you are using equivalence chequing (RTL2Gates) AND your STA is clean AND your design is fully synchronous, then you can skip GL simulation.
But it would give you a warm feeling that your design is doing what it should do. So I would suggest to, at least, run the simplest test in the netlist too.

BUT say your STA scripts have some bugs. Then GL simulations would most likely reveal them.

So it can be used as a cross-check to STA or even to FV

If you have the resources available just do it!!!!

cheers
 

Re: The difference between functional and gate-level verific

1. If we use SDF file, which is generated after synthesis for Gate level simulation, will not give actual delay , But with the use of sdf file which is generated after place and route gives actual delays of design (gate delay + net delay).

---Subjected to FPGA flow...I dont know abt ASIC.. is it same???....PLease correct me if im wrong.....


2. STA is synthesis issue..so we do STA during synthesis ?????? not after that???
------I think during synthesis only not after that..


3. STA comes in front-end OR Back-end??? ---
-----front-end , not back-end..

Please comment.....
 

You can verify function with Stimuls same as rtl simulation, or you can use hspice/star-simxt verfiy function in transistor level netlist.
 

Re: The difference between functional and gate-level verific

1 . If we use SDF file, which is generated after synthesis for Gate level simulation, will not give actual delay , But with the use of sdf file which is generated after place and route gives actual delays of design (gate delay + net delay).

---Subjected to FPGA flow...I dont know abt ASIC.. is it same???....PLease correct me if im wrong.....


2. STA is synthesis issue..so we do STA during synthesis ?????? not after that???
------I think during synthesis only not after that..
Click to expand...


Right ~ we do GLS using sdf file which is generated after place and route. it gives actual delays of design. And STA be done after place and route.
 

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