Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
A flip flop changes output state upon receipt of a clock edge.
A latch behaves as a real time buffer when the enable is active, and it behaves as a register when the enable is negated. It changes state whenever the enable is asserted.
The main differences between a latch and a flip-flop are that the first are level triggered and the latter are edge triggered and that a latch does not have a clock signal, whereas a flip-flop always does.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
