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How to dump out a vcs file in Verilog simulation?

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ne.me.sis

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verilog task function

How to dump out a vcd file at certain time interval in simulation? Anything wrong with I have done in testbench below? It just don't work, and dump out all the time.

In testbench:

initial
$dumpfile("top.vcd");

initial
$dumpvar("0,top");

initial
begin
#1000 $dumpon;
#10000 $dumpoff;
end

initial
$dumpall;
 

Re: Verilog Task Function

Checkout this!

Code: 
initial begin
      $dumpfile("top.vcd");
      #100 $dumpvars(0,top);
      #100 $dumpoff;
      #100 $dumpall;
      $dumpon;
   end
 

Re: Verilog Task Function

initial begin
$dumpfile("top.vcd");
#100 $dumpvars(0,top); // Here Replace #100 by whatever time you need.
end
 

Re: Verilog Task Function

wait for simulation time and put $stop after that.
 

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