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It depends on many factors:
- FPGA/CPLD/ASIC vendor (Xilinx, Altera, Actel...)
- freeware or not
- only for modeling or for synthesis too
- operation system
- ...
It depends if u write VHDL in design for ASIC or FPGA.
For ASIC, there are several platforms.
Those using Windows would prefer MentorGraphics ModelSim VHDL PE or SE.
Those using Unix-based, usually Suns Solaris, would prefer Cadence NCLaunch.
For FPGA, there are several solutions.
Those using Xilinx FPGA would best stick to Xilinx ISE.
Those using Altera FPGA would best stick to Quartus II.
Actel and Cypress also have their own VHDL tools.
A general one but not an entirely universal tool for all the above FPGAs is Synplify.
synplify is synthesis engine, synplifypro is also editor , and has other nifty features.
while ISE Has it all in one package : editor, synthesis engine, p@r, simulatio with modelsim xe.
depend on who works for what project !
By myself .... I think @ltera Baseline 10.2 and Altera Advanced Synthesis is very good for whom is the first user......
i prefer Active HDL n if u can then try 6.3 version . its very user friendly . but donno that its freeware or not. coz we got it frm our VLSI Lab for free .
i think it depends on the purpose. if its rtl implementation, then tools like DC, xilinx, altera are okie. if its for simulation purposes or verification, try nc-vhdl, vcs and others.
in general, it doesn't matter which tool is best. its a matter of which tool will provide more features for the given purpose.
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