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rise time and fall time of inverter

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p.sivakumar

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Hi
Both n-mos and p-mos widths are minimum widths(that means we cannot folde it to decrease the rise time ) then
To maintain the equal rise time and fall time to the inverter What are the steps your going to tack ?

Thanks
Sivakumar
 

to maintain rise and fall time width of pmos is generally taken as 2.5 to 3 times that of nmos, as electron velocity is more than holes....

dont know what u mean by minimum pmos/nmos width..

hope this helps,
Prasad
 

Hi
Actually what your explaind is correct but what i am asking is ....

my p-mos and n-mos widths of inverter is same that is .36u for 0.25u technology
p-mos width is 0.36u
n-mos width is 0.36u (these are minimum diff widths for 0.25utech)
we cannot decrease widths below these width because of drc rules
at the same time we cannot increase the widths of p-mos and n-mos beyound these widths because that is my desing according to functionality.that means we should maintain the equal widths for both n-mos and for p-mos .now rise time is more compared to fall time because low mobility carriers in p-mos.

my doubut is ..

What are the different steps you are going to tack to equalise the rise and fall times of particular inverter ?

Thanks
Sivakumar
 

both transistor r of so less size ??? and only 1 contact for each diffusion?

something different, i would also like to know the answer in this situation.

thanks,
Prasad
 

please go through Digital Design by Rabbay , neat explanation is given
 

Hey,
Have u checked it in the layout.B,cos I feel with so less width u can't connect the contact for the out put with the diffusion b'cos the minimum contact width would be greater than that.And further only one contact is not also very reliable.If u really want o push equal rise and fall time u can try with the length of the NMOS little higher than the minimum length.I think that will work as in that case that will compensate for low speed holes .
regards,
pratap
 

Hi,
I dont think it would be trivially possible to do what you want. I have never seen this kind of design where the widths of p-mos an n-mos transistors are kept equal. Usually for any technology library, a constant is fixed which compensates for the mobility difference between carriers in N-MOS and P-MOS. The whole technology library then maintains this ratio between widths of N-MOS and P-MOS.
Hope this helps,
Kr,
Aviral Mittal.
 

Hi
I faced this problem in one the interview.what he asked is .......according to my functionality my p-mos and n-mos widths should maintain
equal(not minimum widths)then how can u equalise the rise and fall times with out changing of W and L values ?

Thanks
Sivakumar
 

you can have a look at the invertor for clock tree synthesis in founday stand cell library, which has very good balance for r/f edge.
 

Hi
I have another methode to do this.U use body ias technique so that the Vt of NMOS will increase .So u will get equal delay as the currents will be the same for both pull up and pull down.
Hope that helps.
 

You can use 3 P transistor in parallel.
 

please can anyone say me how to simulate the delay time in cadence virtuoso by calculator
 

"pd" your explanation seems correct.
I too suggest the same thing.Use body bias to vary the threshold voltage to get equal rise time and fall time.
 

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