self reset digital logic, without power on reset circuit

power on reset circuit

I have a idea to reset digital logic after power on, without power on reset circuit and hard pin reset. The idea is:

design a 64bit counter, when power on, the counter will be in a unknown state, so if the counter!=0, we generate a reset signal, else do nothing. In theory, this logic only error at 1/(2^64) probability. And we can using anothe small counter to shape the reset signal active time to that of we expected.

Any problem?

digital power on reset

suppose its state is 1 on power up it will create problem till it finishes first count and goes to zero.. in case of microprocess design single clock pulse is very important..

so try some other circuit


REgards
Shankar

digital logic reset

I am confused with your idea.

If there is not a power reset signal, why does your logic judge if it need to check the counter and generate the internal reset signal?

And for my opinion, we need to avoid any un-controlled condition. The counter maybe equal to 0 at your ideal state.

power on reset digital

above answer is right for a normal design, but my solution work also.

Normal: design a power on reset circuit, when voltage is greater than a threshold, reset is deactive, else active. Or reset from pin.

My solution: No need to check voltage, but check a counter state. For example, if counter ~= 12345 then we generate a reset signal to reset all other registers and then set the counter to 12345 (thus the reset signal is only one clock cycle pulse), else no reset. Obviously, in (2^64-1)/2^64 probability, this solution can generate a good reset signal.

I know this solution is not by the design rule of digital design, but let's accept is firstly, and then think why not we use it? Thanks. In fact I have no confidence to use it in my design, so let you help me kill it.

digital power on reset logic

It sounds good, but will it work in practice ?
I think maybe we can also use this to generate a enable clock to gate the full chip clock to help the full system not work before reset.

self reset circuit

The probability that the counter is going to wake up at 0 state is actually relatively high for most standard cell libraries out there. The flops are usually designed to favour 0 reset state. If the probability of flop to wake up to 0/1 was really 0.5 your idea would be ok.