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PNP BJT versus PMOS matching

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aryajur

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Below are attached 2 graphs showing the distribution of Vbe of a PNP BJT and Threshold Voltage of a PMOS transistor for a large number of wafer samples. The For the PMOS Threshold Voltage:
Average = 0.648 V
Standard Deviation = 0.0273V

For the Vbe of the PNP BJT:
Average = 689.83mV
Standard Deviation = 1.8384mV

So now the question is, are the PNP transistors better matched or the PMOS transistors better matched? Another way to put it will be, would it be better to make Current mirrors using these PNP transistors or these PMOS transistors?
Although the SD of Vthp is 27mV the current is a square function while the current is a exponential function, so that makes it harder to compare.....
 

mos matching

For a mirror application the current matching is important.

The transconductance is

Gmos=2*ID/VDSAT so the relative current matching is

dID/ID=(2*ID/VDSAT)*dVgs/ID=2*dVgs/VDSAT

Gpnp=IE/VT so the relative current matching is

dIE/IE=(IE/VT)*dVbe/IE=dVbe/VT

If I take your numbers

dID/ID=2*27.3mV/300mV=18.2%

(300mV typical VDSAT for a mirror in VDD<=3V

dIE/IE=1.8384mV/26mV=7.07%

I assume if you compare a possible lateral poly pnp (?) from a CMOS process with a PMOS that the current of the PNP is low (10-40). So you have to use improve mirror circuits to overcome the current mismatches from low beta.
 

    aryajur

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cmos better than bjt

Hey thanks,
So that means the PNP transistors would be better suited for current mirrors. I just didn't understand the last line you wrote:

So you have to use improve mirror circuits to overcome the current mismatches from low beta.

This PNP transistor is a vertical BJT (BiCMOS process) and its Beta is high enough. What if it is low? Why is that making a difference?
 

bjt widlar current

The BJT gets better if you have only 150mV headroom for the mirror. If you have low beta you can use a Widlar mirror which supply the base current of both mirror devices. It has the drawback that instead of a simple diode connection a further device should be added. If the device is a BJT you can decrease the base current affecting the mirror input by 1/beta. At some target performance level the Early voltage come into play.

Who provide a BiCMOS process with vertical PNP?
 

bjt wilson current mirror

Good explanation by rfsystem on this issue.

I just wanted to add that from experience, other factors to decide between PMOS/NMOS or PNP/NPN for current mirrors are the absolute value of the current and the output impedance

1) For low values of current, say less than 50 uA as a rule of thumb, large channel length PMOS would be better than PNP because of the finite beta (which you compensate for in the PNP design). Also, you add degeneration resistor in the Widlar/Wilson current mirror, so in terms of headroom, PMOS is better than PNP.

2) I know from experience that the output impedance (over frequency) of NPN current mirror in better than NMOS current mirror. I'm assuming the same is the case for PNP, PNP would be better than PMOS (have not verified it, though). The impedance issue is critical if you use it as a tail current in differential pair for high frequency applications.

Based on these factors, I would decide between PNP (NPN) or PMOS (NMOS) for a current mirror in a BiCMOS process.


Bharath
 

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