Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Fatal error in VHDL: can't open a file in rb mode

Status
Not open for further replies.

emmos

Member level 2
Joined
Dec 30, 2003
Messages
47
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,288
Activity points
472
hello

I am writing a vhdl program for reading text files and i run it in modelsim but it gives me the following error

** Error: (vsim-7) Failed to open VHDL file "hds_projects/my_project2/my_project2_lib/hdl/file_io.txt" in rb mode.
# No such file or directory. (errno = ENOENT)


why???

plz help

i attached the vhdl code

thanks

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

LIBRARY std;
USE std.TEXTIO.all;

ENTITY file_io IS
END ENTITY file_io;

--
ARCHITECTURE test OF file_io IS
signal done : std_logic := '0'; -- flag set when simulation finished
begin -- test of file_io
done <= '1' after 5 sec; -- probably set via logic, not time

read_file:
process -- read file_io.in (one time at start of simulation)
file my_input : TEXT open READ_MODE is "hds_projects/my_project2/my_project2_lib/hdl/file_io.txt";
variable my_line : LINE;
variable my_input_line : LINE;
begin
write(my_line, string'("reading file"));
writeline(output, my_line);
loop
exit when endfile(my_input);
readline(my_input, my_input_line);
-- process input, possibly set up signals or arrays
writeline(output, my_input_line); -- optional, write to std out
end loop;
wait; -- one shot at time zero,
end process read_file;

write_file:
process (done) is -- write file_io.out (when done goes to '1')
file my_output : TEXT open WRITE_MODE is "hds_projects/my_project2/my_project2_lib/hdl/file_o.txt";
-- above declaration should be in architecture declarations for multiple
variable my_line : LINE;
variable my_output_line : LINE;
begin
if done='1' then
write(my_line, string'("writing file"));
writeline(output, my_line);
write(my_output_line, string'("output from file_io.vhdl"));
writeline(my_output, my_output_line);
-- write(my_output_line, done); -- or any other stuff
writeline(my_output, my_output_line);
end if;
end process write_file;

END ARCHITECTURE test;
 

modelsim failed to open file in rb mode

It appears to me, there is no problem with your code. It seems that you don't have created the file you are trying to read, or it isn't located in the path you are indicating.
 

failed to open vhdl file in rb mode

read modelsim tutorial it helps u to do small project step by step

good luck
 

rb mode+modelsim

i guess u should be sure what permissions you have on the file...if u did create it
also, there maybe a problem with the path...
it is a tiny problem...i hope u can solve it soon
feed us back with what u did

Salma
:D
 

failed to open vhdl file in rb mode.

Your problem seems to be that you are using a relative directory path that is relative to the wrong place.

You should either specify an absolute path name (yuck), or you should reference it from the 'work' directory that the ModelSim compiler creates.

i.e. if the work directory is in:
hds_projects/my_project2/work

you should 'cd' ModelSim to:
hds_projects/my_project2/

and your path name should be:
hdl/file_io.txt

Cheers,

Blowfishie
 

failed to open vhdl file hex in rb mode

dear all,

i still have a problem so i decided to do a smaller program


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

LIBRARY std;
USE std.TEXTIO.all;

ENTITY file_io IS
END ENTITY file_io;

--
ARCHITECTURE r_w_file OF file_io IS
BEGIN
try: process

file ini_file : text open read_mode is "C:/hds_projects/test1/test1_lib/hdl/in_file";
file outo_file : text open write_mode is "C:/hds_projects/test1/test1_lib/hdl/out_file";
variable in_line,out_line : LINE;
variable half : INTEGER;

begin
wait;
while not (endfile(ini_file))
loop
readline (ini_file,in_line);
read (in_line,half);
half := half/2;

write (out_line,half);
writeline(outo_file,out_line);
end loop;
end process try;
END ARCHITECTURE r_w_file;

I put the file in that path the file is named in_file and it contains a no. 22 for reading

the modelsim

it gives me this error

# ** Error: (vsim-7) Failed to open VHDL file "C:/hds_projects/test1/test1_lib/hdl/in_file" in rb mode.
# No such file or directory. (errno = ENOENT)
# Time: 0 ns Iteration: 0 Instance: /file_io

i have read somethings about putting $ infront of the path????

plz help
 

vhdl writeline

Hi emmos,

This should work...
Are don't you have any extension to your files (.txt, .bin, .hex, ....) ?
 

failed to open vhdl file in rb mode.

give extension as .txt and move the file to other location on inside hds_projects..

and edit the code according to that..

it will work


Regards
Shankar
 

failed to open vhdl file in rb mode

May be it is that MTI under Windows uses "\" as directory separator. How about using simple file name such as:

file ini_file : text open read_mode is "in_file";

And make sure you have this file in the curent working dir where you launch MTI from?

Ajeetha, CVC
www.noveldv.com
New Book: A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
https://www.systemverilog.us/
 

modelsim failed to open file in read mode

i dont know if this is true or not, but me myself, never specify a path... i just write ie:
file my_input :
TEXT open READ_MODE is "io.txt"; and then put the file in the same path as other project files....ofcourse i complie everything from ISE7.1 and dont know the exact process of doing it in modelsim....
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top