How to add pull-up /pull-down resistor for FPGA's IO ports

ucf pullup

I want to add a weak pull-down resistor on 3-state output buffers and bidirectional buffers in Xilinx FPGA, I have tried to code it like this:

IOBUF KIO_0 (.O(KIO_I[0]), .IO(KIO[0]), .I(KIO_O[0]), .T(!we));
IOBUF KIO_1 (.O(KIO_I[1]), .IO(KIO[1]), .I(KIO_O[1]), .T(!we));
IOBUF KIO_2 (.O(KIO_I[2]), .IO(KIO[2]), .I(KIO_O[2]), .T(!we));
IOBUF KIO_3 (.O(KIO_I[3]), .IO(KIO[3]), .I(KIO_O[3]), .T(!we));
IOBUF KIO_4 (.O(KIO_I[4]), .IO(KIO[4]), .I(KIO_O[4]), .T(!we));
IOBUF KIO_5 (.O(KIO_I[5]), .IO(KIO[5]), .I(KIO_O[5]), .T(!we));
IOBUF KIO_6 (.O(KIO_I[6]), .IO(KIO[6]), .I(KIO_O[6]), .T(!we));
IOBUF KIO_7 (.O(KIO_I[7]), .IO(KIO[7]), .I(KIO_O[7]), .T(!we));

PULLDOWN pdIO0(.O(KIO[0]));
PULLDOWN pdIO1(.O(KIO[1]));
PULLDOWN pdIO2(.O(KIO[2]));
PULLDOWN pdIO3(.O(KIO[3]));
PULLDOWN pdIO4(.O(KIO[4]));
PULLDOWN pdIO5(.O(KIO[5]));
PULLDOWN pdIO6(.O(KIO[6]));
PULLDOWN pdIO7(.O(KIO[7]));

but it does not work!!!
Can anyone help me? thank you!!!

xilinx pullup

use constraint editor of xilinx ise to add pullup for io signals

xilinx pulldown

thank you kib, can you give me a detailed explanation about the usage of constraint editor ?

fpga pullup

NET "Dat7IO" PULLUP;

pull up the io xilinx

in xilinx ise click on "Assign Package Pins"
Xilinx PACE tool will be launched
on the design object window you will find all the i/o signal
there is a column called termination.
set pullup or pulldown as per ur requirement for the required signal

affecting weak pull down in ise

if ur not using GUI Constraint editor then assign PULLUP or PULLDOWN in the .ucf file (constraint file) where u are assigning your signal to the pin.

pullup fpga

thanks, it works when use pull in constarint file.