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Shift Registers without clock

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sesl33

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I have a question.
What is the circuit for shift register without clock?

Just an example, say I have a verilog code as follows:-

reg [15:0] A, B;
reg [15:0] C;
integer i;

always @(A or B) begin
for (i=0; i < 16; i = i + 1) begin
if (A>B) begin
A = A << 1;
C = 1;
end
else begin
B = B << 1;
C = 1;
end

end

PS: There is no purpose for the circuit description above. Just an example that I cannot visualize on how the digital circuit will look like.
 

It is a shifter without registers.
 

edacw1 said:
It is a shifter without registers.

But, in this case, how does the circuit know when to shift the data?
for the case that a clock exist, data is shifted in every clock cycle.
But, for this case, since there is no clock, how to determine if the data have been shifted in and how to assert that the data shifted in is correct?
 

u have to know what is the transmitter frequency and the receiver freq

for example, if u know that the input is feed into shift register at 5Mhz, the the receiver part at the output will need to receiver at 5Mhz.

since there is no clock, so all the input must be done parallelly, instead of serial
 

yuenkit said:
u have to know what is the transmitter frequency and the receiver freq

for example, if u know that the input is feed into shift register at 5Mhz, the the receiver part at the output will need to receiver at 5Mhz.

since there is no clock, so all the input must be done parallelly, instead of serial

Hi,

First of all, thank you very much for the reply.
So does that mean that the actual circuit that would be synthesized is actually multiplexer and gates?

i.e. for A <= A << 1, we expect a flip-flops when clocking is available. Now that the circuit is in parallel, does it means that it is a selector?

say: A[15] = (A>B) ? A[14]: A[15];
etc.
 

your code will be syntheized to a comparator and a mux chains, no shifter, for >> << is a constant "1".
And also no register is generated.
 

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