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SOC Encounter: .v file is a verilog or synthesized verilog?

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p_shinde

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SOC Encounter

hi,

one of the inputs given to SOC encounter is the .v file, is this a verilog file or synthesized verilog file ?

reply soon, thanks in advance
.
Prasad
 

Re: SOC Encounter

this is usually a netlist file. along with this, u ll be given lef files for hardmacros(usually memories i suppose) and lib files. using these files, the backend process starts.
 

SOC Encounter

yes its a synthesized verilog file
 

SOC Encounter

The .v file is verilog netlist file. It is a synthesized file.
 

Re: SOC Encounter

Yes its synthesized verilog netlist
 

Re: SOC Encounter

it can be gotten from synopsys dc or rtl compiler or buildget ..
 

Re: SOC Encounter

For SOCE 4.2 and before, the design must be given in Verilog gate-leve netlist for P&R.
---------------------------------------------------------------------------------------------

From SOCE 5.2, it has integrated RTL Compiler(RC) inside.
So you can also give the design in Verilog RTL code for logic synthesis.
----------------------------------------------------------------------------------------------
 

Re: SOC Encounter

If the SOC Encounter synthesis RTL codes, will the builtgates be abandon?
 

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