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how to measure clock jitter in designing clock frequency

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kil

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hi all,

i have a question regarding clock jitter

how to measure clock jitter when clock frequency and other related delays that are present in sequential design are given what are the procedure to measure clock jitter

plz do forward related links if u have any

regards
kil:D
 

clock jitter occurs due to variations in crystal oscillator supply voltage.. for synthesis I use a 1-2 % margin of the system clock for clock jitter.
 

I guess we get this from the vendor or use some thumb rules like eda_wiz
 

hi
JITTER is related to the variations in the period.
so to find period to period jitter i will find periods of the clock waveform for specific amount for ex:20 periods.so i will have period1,period2,period3...period20.
MAX absoulte value of (period(N+1)-period(N)) GIVES YOU JITTER.
PANDIT
 

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