lovseed
Member level 2
I am designing an 14-bit DAC. To compensate the systematic gradient errors, i need to control the switching sequence of the MSB current sources.
I am refering to the paper "A 14-bit Intrinsic Accuracy Q^2 Random Walk CMOS DAC"
But I am not quite clear how it implement the decoding logic with a special VHDL implementation using lookup tables.
Anyone know the details?
I am refering to the paper "A 14-bit Intrinsic Accuracy Q^2 Random Walk CMOS DAC"
But I am not quite clear how it implement the decoding logic with a special VHDL implementation using lookup tables.
Anyone know the details?