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Help us with clocks in a count down counter design

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mikejames07

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Clock Design HELP!!!

A classmate and I are designing a count down counter. We have the design for the count down part, we wanted to add a feature that would speed up the counter when a switch was turned on. We basically have two input "clocks", one with regular frequency and one with a multiplied frequency. We just cannot figure out the logic on how to get our design to choose between the two. Any ideas???
 

Re: Clock Design HELP!!!

u can AND one clock with SWITCH and AND the other with SWITCH(bar) and then OR the outputs of the 2 AND gates and the output of this OR gate is the input clock to the counter
 

Clock Design HELP!!!

You just need an enable signal to select the output of 2 counters.

for example:
assign out = (switch)?couter1:couter2;
 

Clock Design HELP!!!

You should use the gated clock as mentioned above, and the glitch between the 2 clock switch must be taken into account.
 

Re: Clock Design HELP!!!

In the context of a bigger circuit, the method of using multiple clocks to speed up the counter by a fixed factor is not a good one. Introducing a new clock in the design always increases the complexity and affects STA, placement and routing, scan insertion and ATPG, reset circuit design etc. It is much simpler to have two different parameter definitions so that depending on the "mode" of the counter it decrements by 1 or say by 10 on every clock edge. You would need to run the counter on the faster of the two clocks. If power saving is a concern and the difference in clock frequencies is very very large (say 1 KHz and 100MHz) then clock multiplexing might be justified.
 

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