Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Generating a 90 degree phase shift clock

Status
Not open for further replies.
C

colette

Newbie level 3
Joined
Apr 7, 2006
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,308
Hi

I have two clocks in the system, 128mhz and 64mhz, I want to generate a 90 degree phase shifted 64 mhz clock. The fpga does not have a pll or dll, any advice would be greatly appreciated
 

colette said:
Hi

I have two clocks in the system, 128mhz and 64mhz, I want to generate a 90 degree phase shifted 64 mhz clock. The fpga does not have a pll or dll, any advice would be greatly appreciated
Click to expand...

This is quite simple if you have a 2X clock (ie, you have 128 MHz already).
Pass the 128 MHz through a clock divider - back-to-back flip flops configured in feedback - refer to any standard book on flip-flop based dividers.
The intermediate node in the divider will have a quadrature (90 deg phase shifted) version of the 64 MHz clock and the other node will have the 0 degree reference for the 64 MHz clock.
 
  • Like
Reactions: Steva

    C

    colette

    Points: 2
    Helpful Answer Positive Rating
    S

    Steva

    Points: 2
    Helpful Answer Positive Rating
Hi

Am I correct in assuming that both fflops are clocked from 128mhz, the connection to the D input to the first fflop is the complementary o/p of the second fflop and the Q o/p of the first fflop is connected to the D input of the second fflop.

Thanks for you help
 

entity clkgen is
port (
128mhz : in std_logic;
64mhz : out std_logic;
shifted_64mhz: out std_logic);
end entity;

architecture arch of clkgen is
signal int1, int2 : std_logic_vector (1 downto 0);
begin
process(128mhz) is
begin
if (128mhz=1 and 128mhz 'event) then
int1 <= int1+1;
end if;

64mhz <= int1(1);

end process;

process(128mhz) is
begin
if (128mhz=0 and 128mhz 'event) then
int2 <= int2+1;
end if;

shifted_64mhz <= int2(1);

end process;

end architecture;
 

Here I have corrected the code!
Code: 
entity clkgen is
  port (
    reset         : in  std_logic;
    128mhz        : in  std_logic;
    64mhz         : out std_logic;
    shifted_64mhz : out std_logic);
end entity;

architecture arch of clkgen is
  signal int1, int2 : std_logic;
begin
  process(128mhz, reset) is
  begin
    if (reset = 1) then
      int1 <= '0';
    elsif (128mhz = 1 and 128mhz 'event) then
      int1 <= not int1;
    end if;
    64mhz <= int1;
  end process;

  process(128mhz, reset) is
  begin
    if (reset = 1) then
      int2 <= '0';
    elsif (128mhz = 0 and 128mhz 'event) then
      int2 <= not int2;
    end if;
    shifted_64mhz <= int2;
  end process;
end architecture;
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top