davyzhu
Advanced Member level 1
Hi all,
I want to read one data @(posedge clock) and compare with my module output.
The data file may contain one million data and very large.
What's the most efficient way to do it?
My boss told me to use $readmemh, but it seems waste RAM.
Does Verilog 2001 support buffered read like in C? Where can I find the definition?
BTW, I use Modelsim 6.
Any suggestions will be appreciated!
Best regards,
Davy
I want to read one data @(posedge clock) and compare with my module output.
The data file may contain one million data and very large.
What's the most efficient way to do it?
My boss told me to use $readmemh, but it seems waste RAM.
Does Verilog 2001 support buffered read like in C? Where can I find the definition?
BTW, I use Modelsim 6.
Any suggestions will be appreciated!
Best regards,
Davy