Modeling high-z output in verilog-A

high-z output

Hi,

How do i model high-z output in verilog-A ?

Currently I'm modeling it to output = 0, but it is causing conflict when i cascode them at top level (error = output connected to another output).

Currently the method i'm using is

:
:
vout = 0;
:
:

V(OUT) <+ vout ;
......


With what value should i replace the '0' with in order to get a high-z output?

Thanks a million for ur help !!!!!

verilog high z output

Zout = 1e+15;
V(OUT) <+ I(OUT) * Zout;

switch modeling verilog-a

Hughes,

Thanks for ur advice. But I'm still having the same problem. It seems that the formula u gave still yeilds a voltage value. How do i model it so that the circuit sees a disconnected output (i.e. high-z state) ?

switch modeling veriloga

A disconnected output also has a voltage value. To see the high-z effect, you should connect another low-z driving source to this node.

verilog high z

hello,
as far as i understand u need to model open circuit , so i think u should make input current equal zero and no conditions on voltage "u confused me a little bit, as what i understand is that V(out)=0 is short cicuit not open circuit ,so plz post the solution that u will find".
btw i think if u just make the output node as a voltage node and not electrical it wont draw any current "not sure".
regards,
a.safwat

Hughes said:

A disconnected output also has a voltage value. To see the high-z effect, you should connect another low-z driving source to this node.

Click to expand...

Can you advise me how do i code this in VerilogA? Thanks

Added after 2 hours 34 minutes:

then again, is there any method to disable output in verilogA?

steve_mac said:

Hughes said:

A disconnected output also has a voltage value. To see the high-z effect, you should connect another low-z driving source to this node.

Click to expand...

Can you advise me how do i code this in VerilogA? Thanks

Click to expand...

Add another module with low Zout. Short the ouput of these two module. If one (and only one in this case) output is in High-Z mode, the voltage at the common output node will be set by the another module. If both output are in low-z mode, the voltage at the common output node will be different with any output voltage when their are no short-connected.

steve_mac said:

then again, is there any method to disable output in verilogA?

Click to expand...

What do you expect by disabling an output terminal. If you put a mechanical switch before the output terminal, when you open the switch, what VOLTAGE VALUE do you expect at the output? It can be any value! For an ideal switch (the off state resistance is infinite) and a non-ideal output terminal (it has parasitic capacitance), the output voltage when the output terminal is disabled (by open the switch) will permantly remain to the value before it is disabled.