Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Verilog 2's Complement Shifter

Status
Not open for further replies.

davyzhu

Advanced Member level 1
Joined
May 23, 2004
Messages
494
Helped
5
Reputation
10
Reaction score
2
Trophy points
1,298
Location
oriental
Activity points
4,436
Hi all,

I am new to Verilog and want to build a 2's Complement Shifter.

I found
%displayb(8'b0001_1000>>2); //Output 0000_0110
%displayb(8'b1001_1000>>2); //Output 0010_0110

So, ">>" is unsigned shift.
How can I build a signed (2's Complement) shift based on >>?
i.e. I want 8'b1001_1000>>2 //Output 1110_0110

Any suggestions will be appreciated!
Best regards,
Davy
 

Its simple you have to write ur function to do that!
Code:
module test;
   function [7:0] arithmatic_shift;
      input [7:0] vec;
      input [2:0] shift;
      begin
         arithmatic_shift = (vec >> shift) | ({{8{vec[7]}},8'b0000_0000} >> shift);
      end
   endfunction // arithmatic_shift
   
        
     
initial begin
   $display("%b",arithmatic_shift (8'b1001_0000, 2 ));
   
end
endmodule
 
the design of nand_gates is ok! i have already check it on dc.
 

why not write as
arithmatic_shift = {{8{vec[7]}},vec} >> shift;
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top