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Logic path delay for mux with enable line

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rahulgbe

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Hi,
I have a basic doubt regarding the timing calculation for a multiplexer with an enable input. The mux is a part of the combinational logic path between a set of input and output registers.
I need to find the maximum logic delay in this path in order to compute the max clock frequency, as well as any hold time violations.
How are the mux 'delay from data' or 'delay from enable' to be used for finding the logic path delay?
 

max operating freq = 1 / { max(path delay from ip to op, path delay from en to op) }

for any circuit this is the way.
 

In fact, the most accurate of the equations that represent the maximum amount of time allowed for your logic circuit to compute the outputs is given by:

T(max delay of combo logic) <= T(clock) – Tsetup – Tc-q – Tskew

Find out from above T(clock) whose inverse will give the max. operating frequency
 

Hey here the max freq would be

1/delay for the mux(enale) ip to op
thats all,

the setup time for the reg should be enough than the delay between the mux.
 

yes i think so
anjali said:
max operating freq = 1 / { max(path delay from ip to op, path delay from en to op) }

for any circuit this is the way.
Click to expand...

MODERATOR ACTION: Warning #3 - Do not make useless posts.
 

If your enable pin will hold constant at operation time .
you can set case analysis 1 enable_pin the do STA , and then set case analysis 0 and do STA again . TA tool will decided the longest path .
If not , just do STA .
 

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