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use two flops as synchronizing flops when siganls cross from clock domain to another clock domain. This ensures that the signals is latche proeprly with second clock. this also ensures the metastable (which generally occurs in these situations) aviodance.
Re: How to synchronize the two clocks running at different f
If you are talking about one clock system receving data generated by another asynchronous clock. You can use aynchronous FIFO. If only one bit handshake signal involved, you can use level synchronizer or pulse-synchronizer.
Re: How to synchronize the two clocks running at different f
A synchroniser circuit used as an intermediate between the two flops (different frequencies). This synchroniser circuit can be modelled using two latches one enabled using clk1 and other being enabled by clk2 . Also variable frequency will affect your hold time constraint drastically if second flop is a t high frequency than the first .
Re: How to synchronize the two clocks running at different f
hi ,
Actually can tell me whether u working in the bread board or in the synthesis segment on a EDA tool..
Anyway the concept is not to unnecessarily optimze the path u have designed between two flops by the tool.. U are in look out for commands do tell i will mail that.
u can use synchroniser circuit constituting latches.. but jus follow the path carefully including all the possible combination paths also and compute timing manually not to violate set up and hold time..
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