Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Asynchronous Flip Flop Design?

Status
Not open for further replies.
E

electronicman

Member level 3
Joined
Nov 7, 2004
Messages
60
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
476
Hi
What ara the methodologies that we can use to design Asynchrous Flip Flop?
the design methodologies for synchrous Flip Flop are understandable and easy like
using FSM .....
 

Using the Asyn. reset method?
 

Why do you need to have an asynchronous flip-flop?
 

VHDL for

ENTITY flip_flop IS
PORT(
set : IN STD_LOGIC;
reset : IN STD_LOGIC;
data : IN STD_LOGIC;
clock : IN STD_LOGIC;
q : OUT STD_LOGIC;
nq : OUT STD_LOGIC
}
END flip_flop;

ARCHITECTURE beh OF flip_flop IS
SIGNAL qq : STD_LOGIC;
BEGIN
nq <= NOT qq;
q <= qq;
PROCESS(reset, set,data,clock)
BEGIN
IF reset = '1' THEN
qq <= '0'; -- asynchronous reset
ELSIF set = '1' THEN
qq <= '1'; -- asynchronous set
ELSIF clock'EVENT AND clock = '1' THEN
qq <= data;
END IF;
END PROCESS;
END beh;

Best regards :)
 

try searching for "sequential logic"
 

i assume u mean to make asynchronous counters or dividers....Use T-flip flops and external combinational logic to provide delays...look again whether u want synchronous or asynchronous...because in async case u will have to take a lot of care about delays
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top