Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Shared Variable and Variable (VHDL)?

Status
Not open for further replies.
M

Mirzaaur

Member level 2
Joined
Aug 5, 2005
Messages
50
Helped
3
Reputation
6
Reaction score
0
Trophy points
1,286
Activity points
1,690
shared variable vhdl

hi all,
can anybody please guide me abuout the difference of shared variable in architecture and a normal variable with in proess after synthesis?
I mean shared variable can be accessed from different proessess but variable is local to a process, how they are configured after synthesis?
thanks for your time,

mirzaaur
 

vhdl variable synthesis

If you want to share your variable,
use the generic in the entity....
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top