Mirzaaur
Member level 2
shared variable vhdl
hi all,
can anybody please guide me abuout the difference of shared variable in architecture and a normal variable with in proess after synthesis?
I mean shared variable can be accessed from different proessess but variable is local to a process, how they are configured after synthesis?
thanks for your time,
mirzaaur
hi all,
can anybody please guide me abuout the difference of shared variable in architecture and a normal variable with in proess after synthesis?
I mean shared variable can be accessed from different proessess but variable is local to a process, how they are configured after synthesis?
thanks for your time,
mirzaaur