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how to improve timing?

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arbalez

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is the timing performance merely depends on the code written? how to improve the timing performance?

everytime i synthesize my code, the timing requirement is usually not met. i'm using quartusII.
 

The timing is mainly depended on the code.
But you can improve your timing by set your FPGA's speed grade,
And set some constraints on I/O of your code .
 

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    arbalez

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Some techniques to increase speed: Use pipelining, short carry chains, short routes, and low fanout.
 

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    arbalez

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Hi arbalez,

Yes, your code is the key. But you can also fix some small vilation by upsize cell,

rerouting, change the datapath structre.
 

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    arbalez

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how about partitioning the logics into managable blocks, does it help (improve the timing)?
 

arbalez said:
how about partitioning the logics into managable blocks, does it help (improve the timing)?
Click to expand...
If that results in shorter routes, then probably yes. In one of my projects, the Xilinx FPGA placer wanted to arrange my large multi-stage design as one big bowl of spaghetti. The result was numerous long routes and hopeless timing. So, I applied location constraints to my stages, and then the tools had no problem meeting my timing, and finished much sooner.
 

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    arbalez

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Alos all of the FPGA makers has app notes it calll HDL coding styles, Xilinx xas section in there ISE documentation, it is around 100 pages look there as well
 

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