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how to write the below verilog code in vhdl

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tarkyss

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how to write aggregate in vhdl

b=a{1'b1};
a is a constant defined with 'define
b is std_logic_vector
for example
a=4
then
b=1111
 

I think this would work if a is a constant predefined in a package or something

signal b : std_logic_vector (a-1 downto 0);

for i in 0 to a-1 loop
b(i)<='1';
end loop;


hope it would help;-)
 

As mentioned above, you should use the constant a in the definition of b:

signal b : std_logic_vector (a-1 downto 0);

Then there is no need anymore to use a, you can just write:

b <= (others=>'1');

Look for "aggregate" in any good VHDL tutorial.
 

or simply

signal b : std_logic_vector(a-1 downto 0) := (others =>'1');
 

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