Clock divider by 3 with 50% duty cycle?

1. clock divider by 3

Hi all,

How to Build a Clock divider by 3 with 50% duty cycle?
Input and output are listed below.

Clkin
__--__--__--__--__--__--
Clkout
______------______------

Any suggestions will be appreciated!
Best regards,
Davy

2. divide by 3 clock

First you have to double input frequency, and then divide it by 3.
then divide it by 2 to produce 50% duty.
for doubling input frequency simply put one delay (such as RC, or buffer gates)
for example 20nS, then XOR input frequency and delayed one, you get 2x multiplayer.

Regards
Davood Amerion

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Below is a circuit that divides incomming wave by 3 with 50% duty cycle ..
Reards,
IanP

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4. clock divide by 3

I prefer Davood Amerion's method,
that would avoid clock glitching.

hi,IanP
can you assure there is no glitching in your combinational source of clock?

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5. divider by 3

It looks glitch-free. It's from a Xilinx app note "Unusual Clock Dividers":
http://www.xilinx.com/xcell/xl33/xl33_30.pdf

The author repeatedly warns about possible simulator problems, but I have no problem simulating it in Verilog/ModelSim.

Both of these methods assume the input clock has 50% duty cycle, or else the output won't be symmetrical.

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6. divide clock by 3

Hi Davood,

Thank you
What's "and then divide it by 3." mean?
Is it 50% duty?

Any suggestions will be appreciated!
Best regards,
Davy

7. divide by 3 circuit with 50 duty cycle

The "divide it by 3" can be just an ordinary two-bit counter that goes 0,1,2,0,1,2,...

After doing those steps, you would have signals like this. For the output to have 50% duty cycle, the input clock must also have 50% duty cycle.

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8. divide by 3 with 50 duty cycle

Originally Posted by Davood Amerion
First you have to double input frequency, and then divide it by 3.
then divide it by 2 to produce 50% duty.
for doubling input frequency simply put one delay (such as RC, or buffer gates)
for example 20nS, then XOR input frequency and delayed one, you get 2x multiplayer.

Regards
Davood Amerion
why dont we divide by 3 directly insted of multipliying by2, then divide by 3, and then divide by 2.

9. clock divided by 3

Dear davyzhu,
I think the echo47's answer is complete.

Dear anjali
Because when we directly divide by 3 we can't get 50% duty (insted we get 33.3% duty)

Regards

10. clock divide 3

hai davood, we can get 50% duty cycle even by directly DIVIDE BY 3. by using 2 couters (one posedge triggered & one negedge triggered) & once total count equals 3, output clk need to be toggled. i followed int his way, instead of multiplying by 2, then divide by 3, then divide by 2.

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11. divider 3

Hi echo47,

Why not go directly from "XOR" to "Divide by 6"?

Best regards,
Davy

12. unusual clock dividers

oh, thanks to echo47 ,
your design is glitching free,the combinational based latch is great!

13. clock dividers

You guys are giving my too much credit. ;)

I drew the timing diagram to illustrate the suggestion by Davood Amerion.

The latch-based design was suggest by IanP. The design is from "Unusual Clock Dividers" by a Xilinx applications engineer.

davyzhu, an ordinary divide-by-6 counter that goes 0,1,2,3,4,5,0,1,2,3,4,5,... wouldn't have 50% duty cycle. By separating the counter into divide-by-3 and divide-by-2, you get 50%. (Actually, this still is a divide-by-6 counter, but with a funny count sequence.)

Someone asked me which program I used to draw that timing diagram. It's just lines drawn with a CAD program. I used good old OrCAD SDT for DOS. I still use it for large project schematics. I prefer it over all the modern tools.

14. esnips + clock dividers made easy

Here is one more ckt in verilog!!
Code:
```module clk_div3(clk,clk_out);
input clk;
output      clk_out;

reg [1:0]   cnt_p, cnt_n;
wire [1:0]   cnt_p_nx, cnt_n_nx;

initial begin
cnt_p = 2'b11;
cnt_n = 2'b11;
end

assign clk_out = cnt_p[0] | cnt_n[0];
assign cnt_p_nx = {cnt_p[0],~(cnt_p[0] | cnt_p[1])};
assign cnt_n_nx = {cnt_n[0],~(cnt_n[0] | cnt_n[1])};

always @(posedge clk)
cnt_p <= cnt_p_nx;
always @(negedge clk)
cnt_n <= cnt_n_nx;

endmodule // clk_div3```
You can add reset signal to remove the initial statement!

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15. 2/3 divider 50% duty

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16. verilog clock divider 50 duty cycle

Thanks. it is useful for me
Originally Posted by nand_gates
Here is one more ckt in verilog!!
Code:
```module clk_div3(clk,clk_out);
input clk;
output      clk_out;

reg [1:0]   cnt_p, cnt_n;
wire [1:0]   cnt_p_nx, cnt_n_nx;

initial begin
cnt_p = 2'b11;
cnt_n = 2'b11;
end

assign clk_out = cnt_p[0] | cnt_n[0];
assign cnt_p_nx = {cnt_p[0],~(cnt_p[0] | cnt_p[1])};
assign cnt_n_nx = {cnt_n[0],~(cnt_n[0] | cnt_n[1])};

always @(posedge clk)
cnt_p <= cnt_p_nx;
always @(negedge clk)
cnt_n <= cnt_n_nx;

endmodule // clk_div3```
You can add reset signal to remove the initial statement!

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17. clock divided by 3 circuit

Check this paper as well

http://www.edaboard.com/ftopic101951.html

Maybe it is the same as the one by tut.

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18. xilinx application note digital clock divider

If simplicity of design strikes you, then here's a solution.

If i have a 3 bit ring counter preloaded with a value 001, then I tap the output from any point, I'd have a divide-by-three 33% duty cycle output.

If i have another 3 bit-ring counter preloaded with same value 001, but clocked on the negative edge of the clock, I'd have another divide-by-three 33% duty cycle output with phase shift of 90 degree wrt the first output.

I OR these two outputs and I get a divide-by-three 50% duty cycle output. Am i right?

•

Yes that would give a 50% duty cycle (assuming the input clock is square), however I wouldn't say a six-flop solution is "simplicity of design". ;)

By the way, if those two counters should ever fall out of sync (for example by a noise glitch or cosmic ray hit), then they would stay that way forever. I recommend using self-synchronizing logic wherever possible.

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20. clk divider 3

Just so that i understand the comment. Is Davood Amerion's solution the best available? Aren't there any issues in that circuit to produce 2x frequency square waves from a XOR gate and delay elements? Isn't designing the delay element more involved than putting six standard flops? I ask this so that i get the perspective...

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