Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to generate FSM for a 3 but parity generator?

Status
Not open for further replies.
P

preet

Advanced Member level 4
Joined
Jan 10, 2005
Messages
112
Helped
7
Reputation
14
Reaction score
5
Trophy points
1,298
Activity points
908
how to model FSM

i am not able to generate FSM for a three bit parity generator which generate a one if it found odd one's on the three consecutive clocks. can any body help me

i have made the above using shift reg but want to know how to do it using FSM

Regards,
Preet
 

Re: how to model FSM

you dont know the coding style for FSM, or you just need someone to give you the state diagram for this operation?
 

Re: how to model FSM

just wanted to know state diagram
 

Re: how to model FSM

Are you need a VHDL-FSM source?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top