abhishek_elec
Junior Member level 1
I have a logic which selects CLK or CLK_invert based on a select signal.
If select = 1 then, o/p => CLK
else o/p => CLK_invert
When the clock switches from one to the other, what is the way to avoid the glitch.
If select = 1 then, o/p => CLK
else o/p => CLK_invert
When the clock switches from one to the other, what is the way to avoid the glitch.