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asking about xilinx area optimization

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genmadow

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i'm working on xilinx ise v6 ...i'm using achain of inverters..the nomber of inveters is even..but ise collapse all inverters and delete them..
how can i enforce ise to keep this inverters as they are... i know there is a way on constraints..but i don't know this..
 

See KEEP in the Constraints Guide. For example:
Code: 
module top (in, out);
  input         in;
  wire    [7:0] chain;  // synthesis attribute KEEP chain TRUE
  output        out;

  assign {out,chain} = {chain[7],~chain[6:0],~in};
endmodule
 

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