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LVDS DC specifications - single ended signal

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There are two pins on my FPGA chip defined as LVDS signals, and I have attached the specs from the datasheet. the supply voltage on my chip is 3.3V.

my question is if I provide a single ended signal 0-2.4 on the pin ( only one of them is high at any point of time) will it hurt the chip as to the DC specs ? It was a mistake on my part connecting the single ended signals to the lvds defined pins, the chip is ignoring the signals, so logic is not a problem, i want to know if it will damage the chip ?
 

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