What is clock skew and max insertion delay?

why clock tree needed in synchronous asic design?
what is clock skew?
how to improve clock skew?
what is max insertion delay?
how to improve max insertion delay?

Re: about clock skew?

Ans to What is Clock Skew ?
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In circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This is typically due to two causes. The first is a material flaw, which causes a signal to travel faster or slower than expected. The second is distance: if the signal has to travel the entire length of a circuit, it will likely (depending on the circuit's size) arrive at different parts of the circuit at different times.

--ans from wiki.

However, purposely skewing clock arrivals to produce useful skew can achieve timing closure and reduce area at the same time.

And finally leave most part of these jobs to beckend tools .

B/R

Re: about clock skew?

why clock tree needed in synchronous asic design?
what is clock skew?
how to improve clock skew?
what is max insertion delay?
how to improve max insertion delay?

Click to expand...

Clock tree is needed to ensure that the clock signal (from the clock source to logic cells) are synchronised at the same time with the same clock delay.

Clock skew is the variation of arrival time (of the clock signal) to the destination logic cell using the same clock source. Clock skew is due to (1) variation in the RC of the clock interconnect due to the geometrical layout of the length and width, (2) process variation in permittivity and thickness (due to the actual fabrication of the interconnect), thus causes imperfection.

To improve clock skew,
1. Use clock tree, with branches as short as possible to reduce R and C, and using wider width for the higher branches closer to the clock source.
2. Use a DLL (delay lock loop).
3. Avoid using clock interconnect over many layers. Try to design the clock interconnect on the same metal layer or within 2 layers in order to reduce vertical resistance due to vias, which is highly resistive.

Maximum insertion delay = setup time + hold time + maximum propagation delay of the logic cell + maximum time of flight (propagation delay of the interconnect)

To improve max insertion delay,
1. Reduce maximum time of flight
2. Reduce propagation delay of logic cell
3. Reduce critical path in the logic cell
4. Alternatively, expand maximum insertion delay by re-timing.

about clock skew?

How to design a DLL (delay lock loop) in FPGA?

Re: about clock skew?

In actual condition , the clock is different from the ideal condition .

There are two problems about the clock timing : skew and jitter.

Skew is due to internect delay . Jitter is due to noise .

Re: about clock skew?

How to design a DLL (delay lock loop) in FPGA?

Click to expand...

Usally they are already there u need to instaniate them, check up the documentation of your device . You should able to find it.

Re: about clock skew?

In synchronous design, there are two variables to effect your timing, one is data rising time in flip flop input and another is clock rising time. So in synthesis stage, we always need to build clock tree to fix one variables in timing problem.

Re: about clock skew?

why clock tree needed in synchronous asic design?
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two reasons:
1. to maintain a reasonable rising time of the clock signal
2. to help reduce clock skew

what is clock skew?
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clock skew is the the difference of clock arriving time at the DFF's clock pin

how to improve clock skew?
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use a clock tree

what is max insertion delay?
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max insertion delay is the longest delay from the clock source point to the DFF clock pin in a clock network

how to improve max insertion delay?
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max insertion delay depends on several facts,
1. the number of DFFs the clock is driving
2. the die area the DFFs scattered
to reduce masx insertion delay, you need to reduce the area, minizie the number of DFFs that driven by a single clock, this may lead to changing your clocking strategy.