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about the design of 74192 synchronous up down counter

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preet

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74192 synchronous counter

hi all,
i am trying to design 74192 counter in VHDL but i am unable to understand how to genrate o/p, because as in datasheet they are trying to say--

when countup is having clk and countdn is kept high counter counts in up direction
when countup is high and countdn is having clk then counter counts in dn direction

and they are saying that counter is positive edge triggerd.

please help me to model the above one.

preet
 

It is positive edge triggered, but it is a somewhat strange chip.
Maybe you need a better data sheet:
**broken link removed**
 

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