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ASIC synthesis & FPGA synthesis

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anjali

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hello,
i have done ASIC synthesis on my design using dc. and i have done FPGA synthesis using synplifyPro on the same design.

i have simulated the ASIC synthesized netlist & all test vectors are passed. and i have simulated the FPGA synthesized netlist, but in this case, some test vectors are failed.

can anybody explain, why it is so?
 

Anjali, You will need to be somewhat more specific about the Test Vectors that failed on SynplifyPro and the warnings or errors thus generated. Reason being DC and Synplify use different optimization strategies. And FPGAs have got some restrictions regarding the RTL which is to be synthesized. So, You should look for the constraints, Optimzation goals, Libraries used and Synthesis properties.
 

I think the constraints, or library is difference between asic and fpga
 

Hi anajali,
so ur post synthesis simulations failed.
but again, whether the behavior simulations were working correct?
 

asic is different to fpga, the netlist passed on asic can not be passed on fpga for ever because the fpga source limitation.
 

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