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mos difference of parallel-series and series-parallel

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alvays

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nmos in series and parallel

Does anybody know difference about that in current mirror applications
It is illustrated in the figure below
 

It's a small difference: first picture has a wire less than second. In simulations won't affect functioning.
 

or first circuit has less parasitic capacitance than the second one.
 

I think there are some differences in AC characteristic,
but the same in DC.
 

The circuits schematic are the same ,but layout engineer think that it is different.

Layout engineer will draw 2 type of these 2 circuit,
So the wafer out performance are difference.
 

Almost the same. But in common-centroid layout design, the first one may have simpler metal wire connections.
 

As some of your opinions,the former one may be better as the parasitic capacitance concerned.
I was just not sure if this would misfunction.
Now can you please tell me to what extent the former one is used. Can I use it instead of the latter
wherever the multipliers exist?
 

1)How about the noise performance?
2)Where you find it, in other words, what's the applicatoin?
 

First schematic have 7 nets, second one have 6 nets. There are rules for LVS which allows them to be similar. The first is easier to layout because it does not require one connection. If the application is a cascode current source also mismatch is not improved because it is defined by the lower part. All other effects does not differ.
 

In terms of nosie, I have calculated it, no mater the flicker noise or thermal noise,
the two cases are with the same noise. Very clever, rfsystem, how do you get
this knid of intuition?
 

29 years analog design
13 years analog ic design
eeng+math edu
 

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