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What happens when we specify addition of two nos in HDL?

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pankaj

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Regarding Synthesis

Hello,

What happens generally when we specifying addition of two nos in any hdl,

eg. a : In Std_logic_vector(31 Downto 0);
b : In Std_logic_vector(31 downto 0);
sum : Out Std_Logic_vector(31 Downto 0)

sum <= a + b;

Will the synthesizer synthesize the adder using ripple carry or carry-lookahead. Specifically what does Xilinx ISE7.1i will do

Pankaj
 

Re: Regarding Synthesis

It depends on what kind of contrains you add and the tools you are using...

Just try and look the result.
 

Regarding Synthesis

Hi,
mostly it will be a ripple carry adder. But it you see the architecture of the devices you will see that they have dedicated carry propagation path in each CLB so the carry propagation delay is quite less.

Best Regards,
 

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