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200MHz on Altera's Cyclone

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blue_phoenix

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Hello,
Does anybody know how can I increase the maximum frequency input for EP1C3T144-8. This is what I currently have. I need to operate at 200MHz. The datasheet indicated that using a 16-bit counter, the maximum clock can reach more then 200MHz. But I'm afraid the my design will not operate at 200MHz.

Please help me.

Thanks in advance.
~blue phoenix~
 

200MHz on @ltera's Cyclone

Don't afraid. If you need to operate at frequency, that more than your design current frequency, you should to use the pipeline techniques. The pipeline registers break the critical path in your desing, and the design operate frequency are increase. The critical path you can see in the timing analyzer (Quartus II).
 

thanks bpu,

I know pipelining, but i don't know how to implement it correctly. Do you know any references I could use to improve my knwoledge in pipelining? I do not know VHDL, but I know VERILOG HDL. I am also used to using Logic Schematic Entry.

This will be a big help because we will be moving our design to a much frequencies.


Thanks in advance
~blue_phoenix~
 

for example, look here

h**p://engr.smu.edu/~mitch/class/5387/week8/pipeline.pdf

the pipeline technique don't depend of HDL, you can apply it in VHDL, Verilog HDL, AHDL, or in Logic Schematic Entry.

don't remember, that all pipelined units in design insert delay. accordingly you should insert the registes in all units, which works in parallel with pipelined units

Added after 19 minutes:

i'm paint the simple example. see the image
 

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