System C, System verilog, or Vera

vera verilog

Does anyone can tell me, System C, System verilog, and Vera, which one is best, which is most popular, and what's the different among them? Or there are some other Languages are better than all of these three to replace the verilog model coding.

systemc vs systemverilog

Don't forget e/Specman!

The answer is: it depends.

If you are coming from a software backgorund and you want to write a behavioural system model, then SystemC is probably best. SystemC RTL is however horrible, ugly, verbose and unreadable, and you'd bve better using SystemVerilog, in my opinion. It is, however, possible

Vera is a verification langauge only. It also has the disadvantages of being proprietary to one vendor (despite openvera) and cannot be used for RTL, so you always need 2 languages. Also, Synopsys seem to be pushing SystemVerilog more and have incorporated much of the vera functionality into SV anyway. e is a simialr story but with s/Synopsys/Cadence/

SystemVerilog can do it all. It can do RTL well, is great for verilog engineers as it is backwards compatible, and has lots of OO and verification features that make it as good or better than SystemC or Vera for behavioural and verification. However, support for it is still ramping up and not all vendors fully support it yet, and those that do will no doubt have some bugs in their implementations, especially as the official standard for it is not even published yet!

You'll aslo find, however, that you need to pay extra for all these solutions. There is a free SystemC compiler, but it gives poor performance compares to those compilers included in commercial products.

systemc systemverilog

SystemVerilog is best suitable for the engineers who originally utilized Verilog; however it does't restrict you. It can also co-simulate with other language provided the tool vendor supports this. and SystemVerilog provides a DPI to cooperate with C/C++, thus faciliating the calling of SystemVerilog and C within the other language. SystemVerilog is quite suitful for the verification engineer; however it can also ehance the architectural modeling and testing environment.


SystemC is quite useful for the system-level modeling.

VERA is a proprietary language and its function can also be replace by SystemVErilog as an assertion-based language, so it's deemed to die in the near future.


For more information, you can refer to the www.accellera.com!

vera to systemverilog conversion

sigurdwang said:

Does anyone can tell me, System C, System verilog, and Vera, which one is best, which is most popular, and what's the different among them? Or there are some other Languages are better than all of these three to replace the verilog model coding.

Click to expand...

Here is a comprehensive discussion about this :

vera system tasks and functions

system verilog will be the trend, because the system verilog includes the vera and upport by synopsys

c call vera

Thomson said:

SystemVerilog is best suitable for the engineers who originally utilized Verilog; however it does't restrict you. It can also co-simulate with other language provided the tool vendor supports this. and SystemVerilog provides a DPI to cooperate with C/C++, thus faciliating the calling of SystemVerilog and C within the other language. SystemVerilog is quite suitful for the verification engineer; however it can also ehance the architectural modeling and testing environment.

SystemC is quite useful for the system-level modeling.

VERA is a proprietary language and its function can also be replace by SystemVErilog as an assertion-based language, so it's deemed to die in the near future.

For more information, you can refer to the www.accellera.com!

Click to expand...

Hi, Thomson. Can you specify some details of how SystemVerilog cooperatew with
c/c++, and how to efficiently use it for verifiaction without too much human effort for programming and interface design? Do those tools support this well?
thanks

systemverilog for vera

Hello, quake.

SystemVerilog provides a interface named DPI, which can ease the utilization of calling SystemVerilong in C codes and calling C in SystemVerilog. This application doesn't require additional and complex knowledge of the operating mechansim of the simulator and adopts the similar calling syntaxes with normal SystemVerilog tasks. Of course some non-compatible data types require some conversion.

This can faciliate the reuse of original C codes such as the the driver configurating the registers written in C and the input stimulus generation by C using "import" and "export".

call verilog from c

SystemC reduce "Time-to-result" in System-level modeling, specially SystemC TLM. However, SystemC RTL is unacceptable because of verboseness, unreadability, lack of tool for synthesis,....
|=> should use for system level design.

System verilog is good but not common for all.

E - I have never used this one.

VHDL - why not ?

vera to systemverilog data type

Thanks ,Thomson. You mean both call verilog in C and call C in Verilog are supported? right? Can I say this is an advanced feature of systemVerilog compared with verilog+PLI? since we usually call system tasks in C with PLI from
verilog codes, but donnot know how to do that reversely. That means if I have a behavioral model in C to call verilog RTL modules, it can work fluently, is it that way?

best systemc compiler

quake said:

Thanks ,Thomson. You mean both call verilog in C and call C in Verilog are supported? right? Can I say this is an advanced feature of systemVerilog compared with verilog+PLI? since we usually call system tasks in C with PLI from
verilog codes, but donnot know how to do that reversely. That means if I have a behavioral model in C to call verilog RTL modules, it can work fluently, is it that way?

Click to expand...

Yes indeed, one is called "import" and other "export". It is different from PLI, there is still PLI. See LRM from www.systemverilog.org for more.

HTH
Ajeetha
www.noveldv.com

systemverilog system tasks

quake said:

You mean both call verilog in C and call C in Verilog are supported? right? Can I say this is an advanced feature of systemVerilog compared with verilog+PLI? since we usually call system tasks in C with PLI from
verilog codes, but donnot know how to do that reversely. That means if I have a behavioral model in C to call verilog RTL modules, it can work fluently, is it that way?

Click to expand...

Yes! This method will definately improve the simulation performance compared with the PLI,etc. techniques proived by original VCS and other tool vendors.

c model to system verilog model

wad is this languages(systemC, systemverilog, vera) all about??...

how about VHDL & Verilog... y they need to create so many language tht perform the same thing?...

those languages are better than HDL language??

sp