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I like verilog, except for those damn missing generate statements. Yes, I know Verilog2001 has them.
But the good thing about vhdl is type safety, makes them more easily scalable.
Verilog is easier to understand and use. For several years it has been the language of choice for industrial applications that required both simulation and synthesis. It lacks, however, constructs needed for system level specifications. VHDL is more complex, thus difficult to learn and use. However it offers a lot more flexibility of the coding styles and is suitable for handling very complex designs
Pls see the link for complete description
Verilog vs. VHDL: VHDL & Verilog Compared & Contrasted
Plus Modeled Example Written in VHDL, Verilog and C
h**p://www.angelfire.com/in/rajesh52/verilogvhdl.html
verilog takes very less simulation time than the VHDL.
most of the companies uses only verilog HDL.
Verilog is easier for coding as it resemble C language.
Verilog syntax and semantics are very easier to understand
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go for verilog HDL any time if u have to choose b/w Verilog & VHDL
reason being verilog is much easier to learn , less complex and less time consuming
also if u r a beginner go for Palnitkar(for verilog Hdl)
u will find this book on betah.co.il (in Hardware subsection)
u may find it on EdaBoard but u have to search for it
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