reset synchronizer to avoid metastability of async reset

reset synchronizer

Who knows how to implement reset synchronizer to avoid metastability of asynchronized reset? And why asynchronized reset is metastable?

metastability reset

See the following paper!

http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf

Hope this helps!

wiki metastability after reset

Hi zhaoyimiao,
As pointed by nand_gates you can refer to the clifford cummings paper. It is quite nicely explained there. Also you can refer "DIGITAL DESIGNS" by John F. Wakerly . Hope this will help.

Regards,

hi...

i have one doubt that even if we synchronize the reset, then wont there be any problem when that synchronized reset is going in design and reseting a flop in which clock is skewed w.r.t clock used in reset synchronizer....

thanks

hi..
Can metastability be removed using fuzzy logic??
Can we afford transmission time delay of few microseconds to process the signal using fuzzy logic???

Re: reset synchronizer -Digital Synchronizer without Metastability

Thought you might find this interesting if you have not seen it before:


Title: Digital Synchronizer without Metastability
Online Source: Click to View PDF File [PDF Size: 103 KB]
https://www.techbriefs.com/component/content/article/5617Authors: Simle, Robert M.; Cavazos, Jose A.
Abstract: A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.
Collection: NASA
NASA Center: Johnson Space Center
Publication Date: September 2009
Publication Year: 2009
Document ID: 20090032096
Subject Category: TECHNOLOGY UTILIZATION AND SURFACE TRANSPORTATION
Report/Patent Number: MSC-23220-1
Publication Information: NASA Tech Briefs, September 2009; 12; Number of pages = 1
Language: English
Subject Terms: CLOCKS; DIGITAL ELECTRONICS; DISCRIMINATORS; FAILURE; LOGIC CIRCUITS; METASTABLE STATE; PULSE DURATION; SYNCHRONIZERS
Accessibility: Unclassified; Publicly available; Unlimited; Copyright, Distribution as joint owner in the copyright
Document Source: CASI
Updated/Added to NTRS: Sep 11, 2009

zhaoyimiao said:

Who knows how to implement reset synchronizer to avoid metastability of asynchronized reset? And why asynchronized reset is metastable?

Click to expand...

- - - Updated - - -

Title: Digital Synchronizer without Metastability
Online Source: Click to View PDF File [PDF Size: 103 KB]
http://www.techbriefs.com/component/content/article/5617Author: Simle, Robert M.; Cavazos, Jose A.
Abstract: A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.
Collection: NASA
NASA Center: Johnson Space Center
Publication Date: September 2009

- - - Updated - - -

Thought you might find this interesting if you have not seen it before:


Title: Digital Synchronizer without Metastability
Online Source: Click to View PDF File [PDF Size: 103 KB]
http://www.techbriefs.com/component/...e/5617Authors: Simle, Robert M.; Cavazos, Jose A.
Abstract: A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.
Collection: NASA
NASA Center: Johnson Space Center
Publication Date: September 2009
Publication Year: 2009
Document ID: 20090032096
Subject Category: TECHNOLOGY UTILIZATION AND SURFACE TRANSPORTATION
Report/Patent Number: MSC-23220-1
Publication Information: NASA Tech Briefs, September 2009; 12; Number of pages = 1
Language: English
Subject Terms: CLOCKS; DIGITAL ELECTRONICS; DISCRIMINATORS; FAILURE; LOGIC CIRCUITS; METASTABLE STATE; PULSE DURATION; SYNCHRONIZERS
Accessibility: Unclassified; Publicly available; Unlimited; Copyright, Distribution as joint owner in the copyright
Document Source: CASI
Updated/Added to NTRS: Sep 11, 2009


Originally Posted by zhaoyimiao
Who knows how to implement reset synchronizer to avoid metastability of asynchronized reset? And why asynchronized reset is metastable?
- - - Updated - - -

Title: Digital Synchronizer without Metastability
Online Source: Click to View PDF File [PDF Size: 103 KB]
http://www.techbriefs.com/component/content/article/5617Author: Simle, Robert M.; Cavazos, Jose A.
Abstract: A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.
Collection: NASA
NASA Center: Johnson Space Center
Publication Date: September 2009

Hi to put it simple, whenever we have a synchronised circuit with flops having asyn. resets, the resets can be applied at any moment of time, whereas the reset removal should be mandatorily synchronised as it may lead to metastability of other circuit components. The best idea is to sync. resets wrt to the corresponding clock domain so that the reset removal will take place sync. The simple reset sync is a 2-flop sync with the D-input of the first flop connected to the reset and the output conncted to the reset of the other circuit elements, similar to the data-synchronizer. This ensures that any change in the reset will affect the circuit after 2 clk cycles, synchronized perfectly with the clk domain.