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VHDL automated test bench

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jigjack

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hi all,

can someone give me an example of using VHDL for creating a fully automated test environment... that includes protocol checking and scorebording ...

i would also like to learn more about creating the same for verilog.

thanks in advance.
 

jigjack said:
hi all,

can someone give me an example of using VHDL for creating a fully automated test environment... that includes protocol checking and scorebording ...

i would also like to learn more about creating the same for verilog.

thanks in advance.
Take a look at SystemVerilog features, capabilities. A recent book has shown a decent complete example with a sophasticated TB. See:
**broken link removed** for more.

HTH
Aji
http://www.noveldv.com
 

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