jigjack
Member level 1
hi all,
can someone give me an example of using VHDL for creating a fully automated test environment... that includes protocol checking and scorebording ...
i would also like to learn more about creating the same for verilog.
thanks in advance.
can someone give me an example of using VHDL for creating a fully automated test environment... that includes protocol checking and scorebording ...
i would also like to learn more about creating the same for verilog.
thanks in advance.