Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

verilog Z value in expression

Status
Not open for further replies.
P

Prasanna Kumar

Member level 3
Joined
Dec 30, 2004
Messages
58
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,288
Activity points
686
verilog z

is it illegal to use 'z' value in expression, in synthesis point of view?
and in any form inside a clocked always block?
 

z in verilog

Not entirely true ... U can synthesise 'casez ' to produce a priority mux structure . Z indicates undriven state so don't make any calculations based on these ..
 

verilog z value

if u have a Z state in mux it will not work.....
 

z verilog

Z should not be used in internal logic,

because internal tri state gate can increase chip's power consumption and

increase difficulty to DFT. Z only can be used on top IO ports.





Prasanna Kumar said:
is it illegal to use 'z' value in expression, in synthesis point of view?
and in any form inside a clocked always block?
Click to expand...
 

verillog equating z

Hi

What about U (Un-initialized) value of VHDL when converting to verilog.

I have some troubles with VHDL files with 'U' when converting to Verilog.

Does someone have a solution?

tnx
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top