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VHDL Signal Leading Lagging

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shahsali

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How to find out whether Signal A is leading over Signal B and if it is leading then how much it is leading using VHDL.
 

Here is how you can do it!

process (A,B)
variable start_A : time;
variable leading_by : time;
begin
if (A'event) then
start_A := now;
end if;

if (B'event) then
if (start_A < now) then
leading_by := now - start_A;
end if;
end if;
end process;
 

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