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AXI 4 Stream Data Width Converter

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Vlad.

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Hi there,



I need to convert (Upsizing and Downsizing) two AXi 4 Stream Slave and Master. Hence, I want to do the following:

-from 1 byte AXI4 Stream Slave to 50 bytes width;

-from 1 byte AXI4 Stream Master to 4 bytes width


Please note that the 1 byte AXI4 Streams both slave and master are the outputs of an MII ethernet core which runs with 25 MHz, and have only data, ready and valid signals.

I have already used this core. the data width convert, but I have some questions:

1. is this the correct approach to do this task?

2. If the MII runs at 25 MHz, the AXI Data width converter IPs, should run also at 25 MHz?


Thank you,

Vlad
 

1. Yes, but why do you need to convert width? why cant you just process the data in a pipeline? Width conversion is usually done because:
- You are changing clock domains and need to maintain a specific throughout (from fast to slow clock)
- You are limited by the interface required
Otherwise its usually just easiest to use the width thats available

2. Yes - the input at least needs to run a 25MHz.

AXI requires a width that is 2^N bytes. so 1-> 50 wont be possible in available cores. You would have to build a custom IP for it.
 

Hi,

Thanks for your reply.
Yes, I just need to be able to fill an 8 byte register with 1 byte data bus coming from AXI. And also to send 50 bytes to MII with 1 byte data bus.
I will try to do it with pipeline, If I have some problems,I will post again.

Thanks,
vlad
 

Hi again,

I am trying to process data by filling and 64-bit buffer with received data from an 8-bit AXI4 stream master. I started with the following approach, but till now seems to fail to work as I expected.

Code:
---AXI4 stream master---------------------------
signal rx_data      : std_logic_vector(7 downto 0);
signal rx_valid     : std_logic;
signal rx_ready     : std_logic;
---------------------------------------------
constant rx_lengh: integer:=8;        --RX buffer width [bytes] 
signal rx_eth_data:std_logic_vector(rx_lengh*8-1 downto 0):= (others => '0') -- RX  buffer
signal rx_eth_cnt: integer range 0 to rx_lengh+1:=0;

process(system_clk)    -- 100 MHz clk
begin
          if (rst = '1')then
              rx_eth_data<= (others => '0');
              rx_ready <= '0';  
              rx_eth_cnt<=0;                 
       elsif(rising_edge(system_clk))then 
                                                  
                  if (rx_valid = '1')then
                        if(rx_eth_cnt >  rx_lengh-1) then
                           rx_eth_cnt<=0;
                                                
                           else               
                           rx_eth_data(rx_eth_cnt*8+7 downto rx_eth_cnt*8)<= rx_data;
                           rx_eth_cnt<=rx_eth_cnt+1;
                           rx_ready <= '1';
                           end if;
                      else
                     rx_ready <= '0';                    
                   end if; 
                 
                     
end if;
end process;
Please maybe somebody has an idea to fix this.

thanks.
Vlad
 

Have you simulated it? have you got a testbench?
 

Hi Vlad,
Answer to 2.
No, you should use the same clock as you are clocking the Ethernet core. The AXI4 Stream interface to the core uses that clock.
Cheers
 

Hi Vlad,
the AXI4 Stream transfer takes place when both ready and valid is '1'. In this case you look at valid and set ready to '1' and increase the counter.
However the sender waits for ready = '1' before it change data.
So you will read the first byte twice.
I suggest in this case that you should always have ready set to '1' and read data every valid='1'.

Cheers
 

Hi,

@TrickyDicky Not yet, But I am looking at the signals with an external logic analyser and I am trying to figure out where is the problem.
@ MarkPh Thanks for your suggestion, I have implemented it but still not working properly. Data is set correctly in that register, but is changing after some time. I running that process at 100 MHz, and data is coming continuously, 64-bit packed, from a GUI in PC.

I will dig in to that to see were I have the bug.
Thank you,
Vlad
 

Using a logic analyser will be a very slow debug process. I highly recommend you get a testbench up and running.
Also bare in mind that while you must wait for ready = valid = '1' to complete a transaction on the same cycle, valid must NOT wait for ready before being asserted. Ready may be dependent upon valid.
 

my guess is either some off-by-one error. Probably the ready being registered. I don't see why ready can't be always '1' after reset. I'd also implement the buffer as a shift register to be a little more efficient.
 

Hi,

Many thanks for your input. I manage to get it work by adding an counter based case structure and i keep ready always '1'. Now its working fine.

Best,
Vlad
 

Hi,

Many thanks for your input. I manage to get it work by adding an counter based case structure and i keep ready always '1'. Now its working fine.

Best,
Vlad

Hold ready at '1' is fine only if you can absorb data on every clock cycle. If you are feeding into a fifo, you probably need to use some of the fifo control signals in the generation of tready.
 

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