Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi
The delay can be modeled with an exponential tem: exp(-Ts). You can find more explanations in "Modern Control Engineering 4th Ed. - K. Ogata", chapter "6-7 Root Loci for systems with transport lag".
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
