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How do I report timing in Prime TIme using multiple libraries in a combinational cir?

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javierh.santiago

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Greetings,

How can I report timing in prime time using multiple libraries for a combinational circuit?

I am using following commands, where "complete.db" is a library that would consider aging effects in the circuit. So, I would expect that prime time gives me a longer timing (but the optimal clock frequency) in order to ensure reliability after several years.

set link_path " NangateOpenCellLibrary.db complete.db "
read_verilog nBitAdder_netlist.v
link_design nBitAdder_netlist

However, when I do "check_timing" or "report_timing", the tool says "No constrained paths". Does anyone can provide some advises? Seems that I have to indicate some constrains, but as this circuit is pure combinational, I am not sure which ones.

P.S. Netlist is just a simple adder, C = a+b, I just need to start using aging library and prime time prior beginning my research project

Regards,
 

Try to use set_max_delay <value> -from a -to C

Thanks.
Is there a way to calculate the critical path without being too much specific ("a" and "C"), I mean, for this case it works very good. However, for a digital design with multiple ports, How can I get the critical path?
 

You can try this:
set_max_delay 0 -from [all_inputs] -to [all_outputs]
 

If your design, constraints, and scripts are correct, just issuing report_timing with no arguments will give you the critical path. Doesn't matter which libraries are used.
 

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