p and n guard ring to short together?

I would like to discuss an old topic here, since that one is not allowed to submit new post.

From this thread: https://www.edaboard.com/showthread.php?t=359538&highlight=deep+nwell
at the 8th floor, the auther mentioned that the example layout, which short the n and p guard ring. My question is why they don't care about latch-up.

From experience, the p-guard ring nearby the nmos should be short to gnd, and the n-guard ring nearby the pmos should be short to vdd to prevent latch-up.

Thanks.

shanmei said:

... the p-guard ring nearby the nmos should be short to gnd, and the n-guard ring nearby the pmos should be short to vdd to prevent latch-up.

Click to expand...

You are right!

This all depends on the local hookup.

-If- you short N guardring to VDD and P guardring to
VSS/psub! -and- you then short the rings to each
other, then yeah, pop goes the weasel when you put
power to it.

But that "-if-" is your assumption, not a general fact.

Many ESD pad designs incorporate nested, butted
guard rings around each transistor. The built-in N+/P+
junction is a "getter" for minority carriers, depletion
region sweeps them out rapidly (you would like, for
this to prevent any escaping the "moat" and doing
bad things like becoming base current somewhere
unhelpful).

In this case the rings tie to one or the other of the
supplies, but not both, and so there is no supply to
supply short.

Tying rings to the hard supply potentials makes their
depletion region wider and more effective, but then
you have to space them by the minimum ntap to ptap
(N+ to P+ or active to active) rule, and not butted in
same-active. This is pretty variable between foundries,
what's allowed generally and in special ESD-device
cases.